This invention relates to semiconductor integrated circuit fabrication and, more particularly, to an improved process for fabricating MOS devices having lightly doped drain (LDD) and source regions.
Semiconductor integrated circuits are comprised of a plurality of devices which invariably include transistors. Transistors are of two general types, namely bipolar and field effect transistors (FET""S).
FIG. 1 describes a common type N-channel MOSFET structure which is a part of a silicon integrated circuit. This MOSFET comprises a semiconductor substrate 1 such as single crystal or epitaxially grown silicon having a region which has been doped to form a P-well 2. An active area 3 is defined between spaced field oxide regions 4 and 5. A gate region 6 of a conductive material such as polysilicon is separated from the surface of the phosphorous doped substrate by a layer 7 of dielectric material such as silicon dioxide. A conductive interconnect material 8 such as tungsten silicide is formed above and in contact with the gate region 6 for interconnecting the gate to other circuit devices. Implanted into the p-doped region 2 are source 9 and drain 10 regions, commonly formed by ion implanting or diffusing a n-type dopant such as arsenic (As) or phosphorus (P), with the FET channel 11 formed therebetween. A cap layer 12 and sidewall spacer 13 structures of insulating material such as silicon nitride protect the gate structures during processing.
Semiconductor processing techniques as described above as well as variations of the structure described above are well known in the art and can be found in many references. By way of example, reference may be had to Silicon Processing For the VLSI Era, Lattice Press 1990; U.S. Pat. No. 5,573,965 to Chen et al, U.S. Pat. No. 5,679,589 to Lee et al, U.S. Pat. No. 5,721,443 to Zhiqiang, U.S. Pat. No. 5,719,424 to Ahmad et al and U.S. Pat. No. 5,723,352 to Shih et al, all of which are incorporated herein by reference.
With the continuously increasing demand for further miniaturization and device speed, MOSFETS have been scaled to the point where the channel length from source to drain falls below 0.5 micron. As the channel shrinks the electric field in the channel region increases resulting in higher substrate current and short/long term hot electron reliability problems primarily due to a tendency to become trapped in the gate dielectric region. One method which has been employed to partially overcome these problems and increase device reliability and performance of NMOSFETS involves adding a LDD region between the FET channel region 11 and each of the source 9 and drain 10 region. In the past, this has been accomplished by either the implantation of a low dosage of phosphorous to the source 9 region and the drain 10 region to form Nxe2x88x92 regions therein (FIG. 2). Due to the relatively high diffusivity of phosphorous, the Nxe2x88x92 regions formed by phosphorous implantation extend underneath the spacers 13 toward the FET channel area 11 under the gate structure. Subsequently, as shown in FIG. 3, a high dosage As implant creates N+ source 16 and drain 17 regions which supersede most of the lightly doped Nxe2x88x92 regions leaving lightly doped regions 18 and 19 separating the source and drain from the channel. This is what has been called the LDD structure.
However, as devices get still smaller and FET channels are less than 0.4 microns, limitations on fabrication precision result in structures which are far from ideal. Due to the high diffusivity, the phosphorous in the Nxe2x88x92 regions further diffuses into the channel during the subsequent high heat drive process used to create the Nxe2x88x92 source and drain regions. This causes severe short channel problems, results in increased sub-threshold leakage and generally adversely affects device performance and reliability.
An alternative to the phosphorous LDD is to use arsenic to create the LDD structures as proposed by H. R. Grinolds, et al in Reliability and Performance of Submicron LDD NMOSFET""s with buried As n-Impurity Profiles, IEDM Tech Dig., 1985, pp. 246-249 and by C. Y. Wei, et al in Buried and Graded/Buried LDD Structures for Improved Hot Electron Reliability, IEEE Electron Device Lett., vol. EDL-7, pp 6, June 1986. Here, a low dosage As implant is formed prior to formation of the spacer and the N+ implant is performed subsequent to formation of the spacer. While the low diffusivity of arsenic as compared with phosphorous generally results in a more predictable structure which does not suffer the same short channel problems of phosphorous LDD structures, the abrupt ends of the Nxe2x88x92 region below the edges of the gate region creates a maximum electric field (E-field) which is still unsuitable for high performance and high reliability devices due to a hot electron problem. To alleviate this problem, a combination P/As LDD structure has been described where a phosphorous-LDD implant is performed followed by an As-LDD implant. Again, due to the diffusivity of the phosphorous, during subsequent processing the short channel characteristics are degraded. Ahmad et al, in U.S. Pat. No. 5,719,424 describe an alternative process utilizing a low dose arsenic implant to form an Nxe2x88x92 region prior to formation of the gate spacer, followed by the formation of the spacer and then the high temperature high dose N+ arsenic implant. Thereafter, a low dose phosphorous implantation step is employed. This minimizes unwanted phosphorous diffusion which normally takes place when the phosphorous is implanted prior to the N+ arsenic layer. In U.S. Pat. No. 5,723,352 still another combined As/P LDD structure is taught. There, the LDD regions are formed by first ion implanting phosphorous, followed by a blanket ion implantation of arsenic between a FOX region and polysilicon gate region. The device is the annealed to crystallize the metal silicide layer on the polysilicon gate. This is followed by the creation of an insulating spacer on the sidewalls of the gate and then a heavily doped blanket arsenic ion implantation to form N+ source and drain regions with subsequent heat treatment resulting in the overlap of the N+ regions and the LDD regions.
It would therefor be desirable to have a process which produces a sub-half micron MOSFET without improved performance and/or reliability in an efficient and economical manner.
In accordance with the present invention a NMOSFET having a LDD structure is formed on an integrated circuit chip by simultaneously co-implanting low doses of both arsenic and phosphorous in the region of the substrate between the field oxide and a thin LDD spacer on the polysilicon gate prior to the formation of the conventional and relatively thick gate spacer, and prior to N+As implantation.
By co-implanting the arsenic and phosphorous as set forth, we have found that the E-field is reduced, the peak field is moved deeper into the silicon substrate, a broader potential minimum is obtained, hot carrier aging characteristics are improved and TED is reduced. The use of the thin LDD spacer allows conventional device Leff control to be retained. This is achieved while reducing the number of processing steps as compared to prior art LDD structures employing both low arsenic and low phosphorous dopants created in subsequent or sequential processing steps.